1. Technical Field
The present invention relates to a semiconductor device having a buried gate, and more particularly, to a semiconductor device and a method of manufacturing the same, which is capable of forming a metal contact that applies a voltage to a buried gate without a separate additional process and preventing failure due to misalignment in forming a contact.
2. Related Art
A dynamic random access memory (DRAM) of semiconductor devices includes a plurality of unit cells constituting of a capacitor and a transistor. The capacitor is used to store data and the transistor is used to transfer data between the capacitor and a bit line in response to a control signal (a word line) using a semiconductor property in which electrical conductivity changes according to the environment. The transistor is constituted of three parts, that is, a gate, a source and a drain. Charges move between the source and the drain according to the control signal. The charges move between the source and the drain through a channel region using the semiconductor property.
When a conventional transistor is fabricated on a semiconductor substrate, the gate is formed on the semiconductor substrate and then the source and drain are formed by implanting impurities into the semiconductor substrate, thereby forming the channel region between the source and drain below the gate. The transistor having such a horizontal channel region occupies an area of the semiconductor substrate. Since a complicated semiconductor memory device includes a plurality of transistors therein, it is difficult to reduce the total area thereof.
When the unit cell area of the semiconductor memory device is reduced, the number of semiconductor memory devices producible per a wafer increases and productivity can be improved. Various methods of reducing the unit cell area of the semiconductor memory device have been suggested. One of the various methods is using a transistor with a recessed gate, which is formed in a recess formed in a semiconductor substrate, so that a channel region is formed along a contour of the recess. Furthermore, a transistor with a buried gate, which is formed to be entirely buried within a recess, has been studied.
However, when the gate is formed as a buried type, since a step difference between a metal line (MO) and the gate increases, misalignment is likely to occur when a contact is formed to connect the metal line and the gate. The metal contact (MOC) is designed to apply a voltage to the gate. Linewidth of the gate is reduced as the semiconductor device becomes more highly integrated. As a result, misalignment is more likely to occur. When misalignment of the metal line occurs, the contact attacks the device isolation layer and comes in contact with the semiconductor substrate below the device isolation layer. Thereby, a signal (power) to be transferred to the gate is transmitted to the substrate, causing the device to fail.